Program analysis extracts the meaning of a program either from the code itself i. Program analysis results enable safe compiler optimizations and support tools that help developers test, debug and understand code. Modern object-oriented software presents challenges to standard static analysis techniques, including dealing with polymorphism, dynamic class loading, reflection, and the widespread use of libraries and frameworks.
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Framework-based systems present challenges of scalability even to dynamic analysis. In addition, they often involve codes written in different languages e.
Traditional analysis approaches must be modified to deal with these issues. This course will explore the state-of-the-art in program analyses for compilation and software tool building. We will introduce several analyses for object-oriented systems, presenting their similarities and contrasting their differences.
The emphasis will be on reference analysis, which enables construction of good approximations to the execution call structure of a program; thus, it is crucial for subsequent analyses or optimizations to determine method side effects, find objects that escape from their allocating method, eliminate unnecessary synchronizations, etc. Dimensions of these analyses that affect their cost and precision will be contrasted. Both static and dynamic analyses related to high-level optimizations of object-oriented code will be covered, with the emphasis on picking an appropriate analysis for a specific task.
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Recent approaches featuring combined analyses for framework-based systems also will be discussed. The course will cover the following topics, starting with fundamentals and proceeding to current research: Static analysis basics e. The uniprocessor era is over, and the microprocessor industry is now focused on multiple processors on a chip or chip multiprocessors CMPs. With CMPs we are entering a new era of computing in which the main focus is on harnessing and exploiting concurrency.
There are a number of issues to be considered in the design of CMP architectures. These range from achieving high-throughput and low power on commercial server applications that have lots of natural thread-level parallelism to the hardware support for automatic parallelization of sequential applications. One issue that seems clear is that our ability to put multiple cores on a single chip will soon outstrip our ability to write parallel programs. To continue improvements in computer performance and cost we must enable the large body of software developers to easily embrace parallelism.
This course will provide an introduction to CMP architectures and a discussion of key architecture ideas for throughput-driven CMP design, latency-driven CMP design, and support for parallel programming. The design of micro-architectures is deeply affected by technological trends. Current and future micro-architectures will be made of several multithreaded cores sharing memory.
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The memory consistency model is a critical part of the ISA specification of an architecture. It affects programmers as well as designers of machines built for that ISA. In this course we will explore the impact of the memory consistency model on machine design. We will use simple, abstracted models of hardware components such as processors, memory systems and interconnections. Then we use these models to understand the impact of coherence, store atomicity and memory consistency models on the design of hardware components and on their inclusion in systems.
The goal is not to overview all the research on these topics, but rather to present simple examples to illuminate the relation between coherence, store atomicity and memory consistency models at the hardware level. The following topics will be covered over 5 lectures Shared-memory architecture fundamentals Core architecture fundamentals; CMP architecture; systems built with CMPs.
Embedded systems are increasingly the computing fabric that touches our everyday lives. Ownership of cellular telephones, digital cameras, and personal digital music players continues to grow. Already most people drive cars that, at the very least, contain several dozen embedded computers, and at home everyday they use appliances such as printers, televisions, game consoles, DVD players and recorders, and game consoles that contain sophisticated embedded systems.
The sheer volume applications and diversity of processors has placed an enormous strain on compiler writers to provide software development tools that meet the stringent demands of embedded software developers. This course will cover current and emerging compilation techniques for embedded systems. Day 1 presents the general structure of optimizing compilers for embedded applications and provides an overview of the key issues facing embedded compilation systems such as runtime performance, code size, memory performance, power consumption, retargetability, security, and tool chain development.
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Day 2 presents code generation techniques and code transformation techniques to produce code optimized for speed. Day 3 starts a discussion of code transformation techniques for optimizing the memory and energy requirements of an application.
The course concludes on Day 5 with a presentation of software dynamic translation and its use in embedded applications. Processors are omni-present and becoming an indispensable entity. They enable new models of people communication; they provide intelligence replacing human decision taking on low-level and repetitious details; and they help exploiting our creativity by generating worlds, not only for gaming and pleasure but also for exploration of territories incompatible to the spectrum of the human senses.
With each processor comes a compiler. New processors are being developed to satisfy unique combinations of demands on power, area, cycles, and interoperability in a larger system regarding a family of subsets of applications. Those applications are big but usually reasonably well-structured, cooperating in distributed larger systems, exhibiting several relatively independent cooperating sub-applications, each with stacks of software of which the deepest interact intimately with the processors' functionality.
That structure is not there by design but out of necessity, usually the result of the application's history of being extended with support for new interfaces, new protocols, new functionality, grown in an organic way. Reuse in application components is key in achieving the shortest time to market; and when on the market, the application has to match its requirements: functionality, speed, power, etc.
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The same holds for processor and compiler components. The target of compilation tends to grow with what can be combined on a chip, which is typically at least the whole application. Cor91 and. Corella , Mechanizing Set Theory , Crow, J. Owre, N. Rushby, M. Shankar, and. Cox86 and. Cox , Object-oriented Programming : an Evolutionary Approach , Caleiro, C. Sernadas, and A. Caleiro, A. Sernadas, and. Sernadas , Mechanisms for Combining Logics , pp. Sernadas, and C. Dupuy and L. Dowek, G. Felty, C. Huet, C. Murphy et al. Dij68 and. Edsger and. Dijkstra , chapter i : Notes on structured programming , pp.
Dij75 and. Dijkstra , Guarded commands, nondeterminacy and formal derivation of programs , Communications of the ACM , vol. Dij76 and. Dijkstra , A Discipline of Programming , Dahl and K. Dun99 and. Dun02 and. Ehrig and. Luiz, F.